Question: Using minimal number $2$ to $4$ decoder and external gates.

Design circuit.

$F_1=x^{\text{'}}yz+xz$

$F_2=x^{\text{'}}yz+x^{\text{'}}y$

$F_3=x^{\text{'}}{y}^{\text{'}}z+xy$

Question:$-$ Implement with multiplexer a logic circuit whose output $1($High$)$ only when prionity of inputs ABCD is $O($low$).$

Question: Design $7$ segment displays.

$7447$IC$.$

Design decoder outputs AbcdEf

$z$ corresponding inputs we $101010111100110111101111$

d

b$)$ Use minimal number of $2$ inputs NOR gates to implement the Boolen for output $\text{'}{a}^{\text{'}}$ only

Question:

a$)$ Derive flip flop input equations as well as circuit output equations.

b$)$ Derive the state table and state diagrams.

c$)$ This circuit draw using $2$ flipflop use not $jk.$

Question: HDL verilog code for:

a$)$positive edge flip flop.

b$)$jk flip flop designed from D flip flop and gates.