Read the following Verilog module. Do not enter it into your computer.

module lfsr$($R$,$ Reset, Clock, Y$)$;

input $[2$:$0]R$;

input Reset;

input Clock;

output $[2$:$0]Y$;

reg $[2$:$0]Q$;

assign $Y=Q$;

always@ $($posedge Clock$)$

if $($Reset$)$

$QR$;

else

$Q\{Q[1],Q[0]Q[2],Q[2]\}$;

endmodule

A comment on combinatorial vs sequential Verilog: in combinatorial $($also known as continuous$)$ Ver$-$

ilog$,$ we use assign statements to connect wires to gates and other components; the connections are

permanent, so any change in the elements in the right$-$hand side of an assign will be immediately

reflected in the value of the left$-$hand side. In sequential Verilog, operations are synchronized to the

clock, and changes to registers happen only at a positive clock edge. In the above code, we can clearly

see the difference: the statement assign $Y=Q$ tells us that the value of the register $Q$ is continuously

output on port Y$.$ Conversely, operations within the always block are executed on each positive clock

edge, that is$,$ when a discrete new input is provided. Therefore, when we assign a new value to Q$,$ that

change is also reflected in Y$.$

A comment on the syntax: the curly$-$brace notation $\{Q[1],Q[0]Q[2],Q[2]\}$ is used here to

construct a $3-$bit value from three constituent bits, from most to least significant: first $Q[1],$ then

$Q[0]Q[2],$ finally $Q[2].$

In the above module, if we initialize the module by asserting Reset and setting $R$ to $100,$ what sequence

of values will be output on Y over the next five clock cycles? Give your answer as a sequence of six

binary values, starting with $100.$