Question: Read the following Verilog module. Do not enter it into your computer. begin { verbatim } module lfsr ( R , Reset, Clock, Y

Read the following Verilog module. Do not enter it into your computer.
\begin{verbatim}
module lfsr(R, Reset, Clock, Y);
input [2:0] R;
input Reset;
input Clock;
output [2:0] Y;
reg [2:0] Q;
assign Y = Q;
always@ (posedge Clock)
if (Reset)
Q <= R;
else
Q <={Q[1], Q[0]^ Q[2], Q[2]};
endmodule
\end{verbatim}
A comment on combinatorial vs sequential Verilog: in \textbf{combinatorial}(also known as continuous) Verilog, we use \texttt{assign} statements to connect wires to gates and other components; the connections are permanent, so any change in the elements in the right-hand side of an \texttt{assign} will be immediately reflected in the value of the left-hand side. In \textbf{sequential} Verilog, operations are synchronized to the clock, and changes to registers happen only at a positive clock edge. In the above code, we can clearly see the difference: the statement \texttt{assign Y = Q} tells us that the value of the register \texttt{Q} is continuously output on port \texttt{Y}. Conversely, operations within the \texttt{always} block are executed on each positive clock edge, that is, when a discrete new input is provided. Therefore, when we assign a new value to \texttt{Q}, that change is also reflected in \texttt{Y}.
A comment on the syntax: the curly-brace notation \texttt{\{Q[1], Q[0]\^{} Q[2], Q[2]\}} is used here to construct a 3-bit value from three constituent bits, from most to least significant: first \texttt{Q[1]}, then \texttt{Q[0]\^{} Q[2]}, finally \texttt{Q[2]}.
In the above module, if we initialize the module by asserting \texttt{Reset} and setting \texttt{R} to 100, what sequence of values will be output on \texttt{Y} over the next five clock cycles? Give your answer as a sequence of six binary values, starting with 100.

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