Register renaming and scheduling [please answer both questions]

computer architecture

1. (1 point) Assume that latency of ADD.D and SUB.D is 2 cycles, and the latency of MUL.D is 8 cycles. Can you reduce the latency of the program below without modifying the program semantics? Explain your answer, and show the number of cycles needed to finish the program. Note: The instruction latency is the number of pipeline cycles that separate an instruction and a dependent instruction.

SUB.D F8, F10, F14

MUL.D F6, F10, F8

ADD.D F8, F0, F12

2. (1 points) Consider the code below. Use register renaming to eliminate all dependences while maintaining the original program semantics. Assume that additional registers R0, R1, . . . are at your disposal.

ADD.D F6, F0, F8

SUB.D F8, F10, F14

MUL.D F6, F10, F8