Requirement:

In Verilog, design, verify and implement a calculator. It adds, subtracts or multiplies a $6$ bit number to$/$from the current content of its accumulator. It continuously display the input number $($on the first two display digits$)$ and the current content of the accumulator $($on the last three digits of the display$).$ The accumulator's range is from $0$ to $255.$

Description

The heart of the calculator is the CTRL block. It receives commands from the push buttons $($PLUS$,$ MINUS, MULTIPLY or CLEAR$),$ and sends control signals to the datapath. Apart from CTRL there are $6$ registers, one for storing the result $($the accumulator$),$ and one for each of the digits used for display. The inputs shown in red are the control signals generated by the CTRL$.$ The blocks colored in blue are sequential, clocked by the $50MHz$ input clock and initialized$/$cleared by the common reset input. The reset is assimilated to the CLEAR command.

The output display configuration is stored in $5$ registers which are updated cyclically, with a rate of around $100Hz.$ In order to use one BCD converter and one BCD$-$to$-$segment converter, the input and accumulator values, and their digits are multiplexed digit by digit. A simple solution may be based on a counter from which $3$ bits are used to generate the required control signals, as in the figure below: