rite VHDL code for a sequence detector that detects two consecutive $1$s

with a $50\%$ overlap $($e$.$g$.,111$ should detect two sequences$).$ Include:

$($a$)$ Entity declaration.

$($b$)$ Architecture with process statement.

$($c$)$ State signal declarations.

$($d$)$ Reset condition $($asynchronous$).$

$($e$)$ Next state and output logic.