roblem $1$

Consider the following MIPS code.

I$0$: lw $s$1,0($$s$2)$

I$1$: add $s$5,$$s$1,$$s$3$ # $s$5$ :$=$ $s$1+$ $s$3$

I$2$: beq $s$5,$$s$7,$ L$1$ # if $($$s$5=$ $s$7)$ goto L$1$

I$3$: lw $s$3,12($$s$4)$

I$4$: sw $s$5,0($$s$3)$

I$5$: L$1$: sw $s$5,12($$s$4)$

A$)$ Suppose a MIPS processor uses the simple $5-$stage pipeline, where the stages are instruction fetch $($IF$),$ instruction decode and operand fetch $($ID$),$ execute and calculate address $($EX$),$ memory access $($M$),$ and write back $($WB$).$ In addition, suppose that:

The instruction and data cache are unified and can only support one read or write or instruction fetch operation each cycle.

The pipeline does not have $$forwarding$$ hardware. Thus, if an instruction $($i $+1)$ relies on a value written into a register by an instruction $($i$),$ then the execute stage for $($i $+1)$ cannot proceed until the register write stage for $($i$)$ has completed.

In the absence of hazards, a new instruction can be fed to the pipeline every cycle.

Assume the branch is not taken.

How many cycles does this code take to complete? Use the table below.