Setup

time

Hold

time

Clk$-$to$-$Q

Prop. delay

D$-$to$-$Q

Pro. delay

Clk$-$to$-$Q

Cont. delay

D$-$to$-$Q

Cont. delay

Flip$-$flops $65$ ps $30$ ps $50$ ps n$/$a $35$ ps n$/$a

Latches $25$ ps $30$ ps $50$ ps $40$ ps $35$ ps $35$ s

$1.(30$pts$)$ For each of the following sequencing styles, determine the maximum logic

propagation delay available with a $400$ps clock cycle. Assume there is zero clock skew

and no time borrowing takes place.

a$)$ Flip$-$flops.

b$)$ Two$-$phase transparent latches

c$)$ Pulsed latches with $80$ps pulse width

$2.(30$pts$)$ For each of the following sequencing styles, determine the minimum logic

contamination delay in each clock cycle $($or half$-$cycle, for two$-$phase latches$).$ Assume

there is zero clock skew.

a$)$ Flip$-$flops

b$)$ Two$-$phase transparent latches with $50\%$ duty cycle clocks

c$)$ Pulsed latches with $80$ ps pulse width