Simulate the following program by converting each instruction to corresponding machine code. Then store the machine code in memory starting from location $10$ :

$\backslash$table$[[$Memory Address,Contents$],[10,$Load R$0,[20]($instruction$)],[11,$Load R$1,21($instruction$)],[12,$Add R$0,[$R$1]($instruction$)],[13,$load R$1,[22]($instruction$)],[14,$Sub R$1,+8($instruction$)],[15,$Add R$0,$R$1($instruction$)],[16,$Store RO$,[23]($instruction$)],[,],[20,6($data$)],[21,-4($data$)],[22,13($data$)],[23,0($data$)],[24,0($data$)],[,]]$

Verify that it works correctly and the also verify that the result stored at address $24$ is correct. Attach simulation waveform and the Verilog source file.