Single$-$cycle MIPS Processor

$($a$)$ Determine the maximum clock frequency for the single$-$cycle implementation.

Assume that no additional overhead is required beyond the delays specified in the table.

$($b$)$ Calculate CPIAVG for program P$1$ executed on the single$-$cycle implementation.

$($c$)$ What is the instruction latency for the single$-$cycle implementation?

$($d$)$ What is the throughput for the single$-$cycle implementation?