Sketch a transistor-level schematic for a CMOS 4-input NOR gate. Sketch a transistor-level schematic for a compound CMOS logic gate for each of the following functions: Use a combination of CMOS gates (represented by cheir symbols) to generate the following functions from A, B, and C )Y A (buffer) Y-AB+BC+ AC (majority Sketch a transistor-level schematic of a CMOS 3-input XOR gate. You may assume you have both true and complementary versions of the inputs available tGollatuint loric functions. You may assume