solve for $(i=0$;$i<mn\; id="EditorElement\_187813">1</mn><mn\; id="EditorElement\_187814">0</mn><mn\; id="EditorElement\_187815">0</mn><mn\; id="EditorElement\_187816">0</mn>$;$i++)$

$q,a[i]=b[i]+b[i+1]+b[i+2]+b[i+3]$

Both $a-$elements and $b-$elements are $16-$bit long.

There are separate ports for memory read and write. The bandwith of both memory ports is $128$ bits$/$cycle$.$

Hardware implementation.

The circuit is running at $200MHz.$ We use the following adder tree to compute one a$-$element. We use the maximum amount of unrolling.

How many clock cycles are needed to finish the for loop, ignoring the data prefetch for the very first iteration?

How many nanoseconds are needed to finish the for loop?

ns$.$

We use the processor to implement the for loop. The frequency is $1GHz.$ Each iteration takes $15$ instructions. $\frac{C}{P}$I $=1\mathrm{.}5$

How many clock cycles are needed to finish the for loop?

clock cycles.

How many nanoseconds are needed to finish the for loop?

ns$.$

What is speedup for using the pipelined circuit?

$($keep two decimal places in the solution, e$.$g$.,12\mathrm{.}34)$