solve task 2 please

Task 2: ALU Design: We can go one more abstract level in behavioral model of the Full adder design using arithmetic operators as can be shown below: module Four Bit_ALU (X, Y, Cin,, S, Cout); input [3:0] X,Y; input Cin; output [3:01S; output Cout; assign (Cout, S)=X+Y+Cin; endmodule Follow the same to design an ALU that will allow 2 arithmetic and 2 logic basic operations (addition, subtraction, bitwise OR and bitwise AND). The operation is to be selected by a 4 to 1 multiplexer's selector as shown in the circuit below. Where operand1=X and operand2=Y. Function Selector Operation 00 Addition 01 Subtraction 10 Bitwise OR 11 Bitwise AND operandi Example operation: 1010 operund 2 0111 function selection 14 ALU c (catry) -- ALU Oradd) result 0001 The ALU is performing this addition: 1010 + 0111 10001 Write a Verilog code to expand the ALU design to be 32 bit and to incorporate total of 7 operators(invertor, shift left and shift right operators in addition to the lab operations). Note: selection line needs to be 3 bits instead of 2