Specification Implement the Truth Table specified below in verilog by entering your code into the window below. in out 0 1 1 0 0 0 0 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 0 0 0 1 0 circuit.v 1 // Design a circuit that implements the specified truth table 2 3 module circuit(out, in); output out; 5 input [3:0] in; 6 7 endmodule // TT2Verilog Restore original file Save & Grade 2 attempts left Save only 40 points available for this attempt (following attempt is worth: 20)