Specification Implement the Truth Table specified below in verilog by entering your code into the window below. out 1 0 0 in 0000 0001 0010 0011 0100 0101 0110 1 1 1 0 0 0 0 0111 1000 1001 1010 1011 1100 1101 0 0 0 0 1110 0 1111 0 circuit.v V/ Design a circuit that implements the specified truth table 1 2 3 4 5 6 7 module circuit Cout, in); output out; input [3:0] in; endmodule // TT2Verilog Restore original file