Subject : Digital Electronic.

Question 1 (a) A 64K X 16 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select. i. What is the size of each decoder, and how many AND gates are required for decoding an address? Assuming that the RAM cell array is square. ii. Determine the row and column selection lines that are enables when the input address is the binary equivalent of (3200010. (b) Design the block diagram for a 256K x 16 RAM by using a decoder and the 64K x 8 RAM chip as shown in Figure 1. 8 64K X 8 RAM V 8 Input data Output data 16 Address Chip Select Read/Write Figure 1