Question: A 64K 16 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select. (a) Assuming that the RAM

A 64K х 16 RAM chip uses coincident decoding by splitting the internal decoder into row select and column select.

(a) Assuming that the RAM cell array is square, what is the size of each decoder, and how many AND gates are required for decoding an address?

(b) Determine the row and column selection lines that are enabled when the input address is the binary equivalent of (32000)10.

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