A Flip-flop design is shown below with an input, X, and a clock, C. It has been
Question:
A Flip-flop design is shown below with an input, X, and a clock, C.
It has been assumed that the inputs cannot change simultaneously.
INPUTS X,C
00 01 11 10
a a ,0 b, - -,- c,-
b a,- b ,0 d,- -,-
c a,- -,- e,- c ,0
d -,- b ,- d ,0 c,-
e -,- f,- e ,1 g,-
f h ,- f ,1 e ,- -,-
g h ,- - ,- e,- g ,1
h h ,1 b ,- - ,- g ,-
a) Use an implication table and merger diagram to show
that one potential minimum solution is {a,b,d}{c}{efg}{h}. (6 marks)
b) Labelling the minimal states above 1 - 4 respectively
create its minimised flow table. (2 marks)
c) Show that the feedback assignment (F1F2) :
1 - (00), 2 - (01), 3 - ( 11) and 4 - (10) is race free. (3 marks)
d) Using the above assignment develop hazard free logic
expressions for the feedback states. (6 marks)
e) Sketch the Moore model of your minimized solution to part Q2a. (4 marks)
f) From the above work, with explanations, identify :
i) The type of flip-flop shown (2 marks)
ii) The clock type it employs (2 marks)
Probability and Random Processes With Applications to Signal Processing and Communications
ISBN: 978-0123869814
2nd edition
Authors: Scott Miller, Donald Childers