Question: Suppose that your processor has 4MB data cache and its block size is 64B. Physical address to access the memory is 50-bit wide (addr[49:0]). For

Suppose that your processor has 4MB data cache and its block size is 64B. Physical address to access the memory is 50-bit wide (addr[49:0]). For each of the following cache structures, calculate TAG size and inted size.

(a) A direct-mapped cache implementation

(b) A 4-Way set associative cache implementation

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