Suppose there were a MIPS instruction called bcp$,$ which copied a block of words from

one address to another. Assume that this instruction requires that the starting address of the source block is in register $t$1$ and the destination address is in $t$2,$ and the number of words to copy is in $t$3($which is $>0).$ Furthermore, assume that the values of these registers as well as register $t$4$ can be destroyed in executing this instruction $($so that the registers can be used as temporaries to execute the instruction$)$

Below is a MIPS assembly language program to implement block copy with instructions

Loop: lw $t$4,0($$t$1)$

sw $t$4,0($$t$2)$

addi $t$1,$ $t$1,4$

addi $t$2,$ $t$2,4$

addi $t$3,$ $t$3,-1$

bne $t$3,$ $$0,$ Loop

Make a copy of the figure of the multicycle implementation and add to the datapath the necessary support to implement bne instruction. Do you need any modifications to the datapath to support the addi instruction implementation? If so$,$carry out the necessary modification.