Suppose you executed the code below on a $5$ stage$$ in order$$ pipelined system that

does not handle data hazards.

Also, the register file HAS the feature of reading and writing in the same clock cycle $($i$.$e$.$ fast register file $($or$)$ half$-$cycle writeback$).$ For example, if the old value of x$1$ is $10.$ Now, let$$s assume that in Clock Cycle $5($CC$5),$ we are both writing a new value of $20$ to x$1$ and also reading x$1$ in the same clock cycle. Then, the output value from the read would be $20$ courtesy of the fast register file $($or$)$ half$-$cycle writeback feature. This new value of $20$ will be available in x$1$ in CC$5.$

In this context, what will be the final values of registers x$13,$ x$14,$ and x$15$ at the end of this code block?