$\backslash$table$[[$Instruction$,$RegDst,$\backslash$table$[[$ALU$],[$Src$]],\backslash$table$[[$MemTo$],[$Reg$]],\backslash$table$[[$Reg$],[$Write$]],\backslash$table$[[$Mem$],[$Read$]],\backslash$table$[[$Mem$],[$Write$]],$Branch,Jump,$\backslash$table$[[$ALU$],[$OP$[1]]],\backslash$table$[[$ALU$],[$OP$[0]]],,],[$JAL$,,,,,,,,,,,,],[$JR$,,,,,,,,,,,,],[$SLL$,,,,,,,,,,,,],[$SRL$,,,,,,,,,,,,]]|$Modify $($add drawing to the provided figure or draw by yourselves$)$

the following MIPS architecture to add JAL, JR$,$ SLL$,$ SRL instruc ons. JAL instruc on

works similarly to J instruc on but stores next instruc on to $ra $($$$31)$ register.

Therefore, JAL performs two opera ons at the same me: It not only stores the address

of the next instruc on $([$PC$+4])$ in the return address register $($$ra$),$ but also jumps to the

target address similar to the Jump instruc on$.$ JR instruc ons is an R$-$type instruc on

that reads the address for jump from the register $ra and jumps to that par cular

address. Also, decode your JAL, JR$,$ SRL and SLL instruc ons to fill up and add more

control signals to the truth table $($page#$3)$ as you require.$|$