TASK$4(20$ pts$.]$: Design a Verilog model for a counter using a for loop with an output type of integer. The counter should increment from $0$ to $63$ and then start over. Use delay in your loop to update the counter value every $40$ ns$.$ Consider using the loop variable of the for loop to generate your counter value. Write a testbench and simulate your design to verify the functionality using Modelsim!M$.$