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Use the following code fragment:

Loop: LD R2,0(R1) ;load R2 from address 0+R1 DADDI R3,R2,#2 ;R3=R2+2 DADD R2,R2,R3 ;R2=R2+R3 SD 0(R1),R2 ;store R2 at address 0+R1 DSUB R4,R1,R3 ;R4=R1-R3 BNEZ R4,Loop ;branch to Loop if R4=!0

Use the classic RISC five stage integer pipeline and assume all memory accesses take 1 clock cycle.

Show the timing of this instruction sequence for the basic 5-stage RISC pipeline, but without any forwarding or bypassing hardware. Furthermore, assume that a register write at the WB stage happens in the first half of the clock cycle, while a register read at the ID stage happens in the second half of the clock cycle. This means that a write at WB stage can forward value through the register file to a read at the ID stage (trivia: MIPS R2000/R3000 has such a feature).

Use 'F', 'D', 'X', 'M', 'W' for stages, -' for stall, '=' for indicating delayed fetching due to waiting for branch resolution, and 'b' for all other blanks.

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Use the following code fragment from Question 1: Use the classic RISC five stage integer pipeline and assume all memory accesses take 1 clock cycle. Show the timing of this instruction sequence for the basic 5-stage RISC pipeline, but without any forwarding or bypassing hardware. Furthermore, assume that a register write at the WB stage happens in the first half of the clock cycle, while a register read at the ID stage happens in the second half of the clock cycle. This means that a write at WB stage can "forward" value through the register file to a read at the ID stage (trivia: MIPS R2000/R3000 has such a feature). Use ' F ', 'D', 'X, 'M', 'W' for stages, -' for stall, '=' for indicating delayed fetching due to waiting for branch resolution, and 'b' for all other blanks. [For the spacing concern of the Webcourses, the timeline is put in rows and instructions are put in columns. The first column is filled out for your reference]