The aim of this task is to implement a Carry$-$Lookahead Adder $($CLA$)$ in SystemVerilog. The CLA is to add two n bit numbers together. It consists of $$ blocks for k columns each so that n $=-$ k$.$

Except for the testbench, it is not allowed to use addition operators, comparison operators or similar, use only operators from Boolean algebra $($Boolean reduction operators are allowed$).$

Note: You can also receive points for later parts of the task if you were unable to solve previous parts.

A CLA block for k columns is constructed as follows from the blocks RCA, GP and CARRY:

Now implement the parameterized SystemVerilog module cla$\_$block for a k$-$column block of the CLA. Use instances of the modules carry, gp and rca. An implementation of rca is already provided here, you only need to instantiate it$.$

Note: You can compile and test your code with the following command:

Windows: $./$sim$.$bat cla$\_$block, Otherwise: $./$sim$.$sh cla$\_$block

Note: If you do not solve this task, you can use cla$\_$block$\_$filler.sv as an implementation of cla$\_$block for the following tasks. To do this, copy it to cla$\_$block.sv This implementation is correct, but uses addition operators internally and is therefore not a valid solution for this subtask. this subtask.'timescale $1$ns $/1$ns

module cla$\_$block

#$($parameter $K=4//$ Number of columns per CLA block

$($ input logic $[K-1$:$0]A\frac{,}{\frac{?}{?}}$ Operand $A$

input logic $K-1$:$0$ B$,//$ Operand B

input logic C$\_$IN$,//$ Carry$-$In

output logic $[$K$-1$:$0]$ SUM, $//$ Sum

output logic C$\_$OUT$)$; $//$ Carry$-$Out

$/$

endmodule