The combinational circuit below is pipelined at all its inputs and output. The circuit uses one clock. The delays for combinational blocks: $2-$input adder $=2$ns$,3-$input adder $=3$ns$,$ multiplier $=5$ns$,$ absolute $=3$ns$,$ square root $=7$ns$.$ Delays for registers: Setup $=1$ns$,$ propagation$($CQ$)=1$ns $($a$)$ Identify the longest and shortest combinational path. $($b$)$ Find the minimum clock period and the maximum frequency. $($c$)$ Maximally pipeline the circuit, and show all registers $($internal and I$/$O$)$ on the circuit. $($d$)$ What are the period and the frequency in part $($d$)?($e$)$ Find the condition imposed on hold time.