The datapath is modified with SIX changes, labeled (A) -(F) , to support single-cycle memory access and addition instructions:

(A): The Register File is extended with an additional read port, with the address coming from rd, and the data output, R[rd], being driven out to a new busC. (B): Mux busC, busA and ALU output into Memory Address slot, with selection signal Z. (C): Mux ALU output and busB into the Memorys data input slot, with selection signal Y. (D): Add an adder with the MemToReg output as one of the inputs into the adder. (E): Mux busB and Extended Immediate into the second input of the adder, with selection signal W. (F): Mux the MemtoReg output and the adder output, and feed it into the RegFile (busW), with selection signal X. In the modified datapath, you have a total of 12 control signals. Below is a table with alternative control settings:

For each of the following instructions, pick the best option that maximizes the number of dont cares while performing the correct operation. i. memaddr rd rs rt: R[rd] = R[rt] + M[R[rs]] (3 points) Takes the value in register rt, adds it to the value in memory at location given by value of rs, and stores it in register rd. (a) Option #1 (b) Option #3 (c) Option #5 (d) Option #6 (e) None of the above ii. memaddi rt imm rs: R[rt] = SignExtImm + M[R[rs]] (3 points) Takes the value in memory at location given by value of rs, adds it to the immediate, and stores it in register rt. (a) Option #1 (b) Option #2 (c) Option #4 (d) Option #6 (e) None of the above

iii. storeadd rd rs rt: M[R[rd]] = R[rt] + R[rs] (3 points) Takes the value in the register rs, adds it to the value in register rt, and stores it in memory at location given by value of register rd. (a) Option #2 (b) Option #3 (c) Option #4 (d) Option #5 (e) None of the above iv. lw rt imm rs: R[rt] = M[R[rs] + SignExtImm] (3 points) Add the value in the register rs to immediate to obtain a memory location; store the value at that location into register rt. (a) Option #1 (b) Option #3 (c) Option #5 (d) Option #6 (e) None of the above

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