The following assembly language program is being run on a $32$ bit ARM processor that uses

a $16$ word cache with a $4$ word block size. You can assume r$0$ is initialized to zero.

$1drr5,[$ r$0,$ #$0$x$0006$c $]$

$1drr6,[$ r$0,$ #$0$x$000$c$4]$

$1drr7,[$ r$0,$ #$0$x$00060]$

ldr r$8,[$ r$0,$ #$0$x$00088]$

Main memory contents are as follows:

a$)$ For each line of the assembly language program, draw a picture of the cache contents

including entries to the tag and valid bits associated with each set.

b$)$ Assuming that a cache access requires $1$ clock cycle and a main memory access requires

$100$ clock cycles, determine the average memory access time for this program.