The following assembly language program is being run on a $32$ bit ARM processor that uses

an $8$ word cache with a $2$ word block size. You can assume that the contents of r$0$ are zero

and r$6$ is $0$xffffffff$.$

$1drr5,[$ r$0,$ #$0$x$00094]$

str r$6,[$ r$0,$ #$0$x$000$a$8]$

str r$6,[$ r$0,$ #$0$x$000$ac $]$

$1drr7,[$ r$0,$ #$0$x$000$cc $]$

$1drr8,[$ r$0,$ #$0$x$00090]$

Main memory contents are as follows:a$)$ For each line of the assembly language program, draw a picture of the cache contents

including entries to the tag, valid and dirty bits associated with each set.

b$)$ Indicate which lines in the assembly language program result in a main memory write

for both the write$-$though and write$-$back cache managment strategies.

c$)$ Determine the average memory access time for this program under the write$-$through

and write$-$back schemes.

Note:

Hint: For part c$),$ you can't just apply the equation from the notes but will instead

need to calculate it based on the memory accesses performed for each line of code.

For part c$),$ you can assume a main memory read$/$write requires $100$ clock cycles

regardless of how many words are read$/$written$.$ A cache read$/$write requires $1$ clock

cycle. A read and write performed for the same command must be accounted for

separately.