The following codes are equivalent.

$```$

signal a$,$ b$,$ y: std$\_$logic;

$...$

process $($a$,$ b$)$

variable tmp : std$\_$logic ;

begin

tmp :$=\text{'}0\text{'}$;

tmp :$=$ tmp or a;

tmp :$=$ tmp or b;

y tmp;

end process;

$```$

$```$

signal a$,$ b$,$ y$,$tmp: std$\_$logic;

$...$

process $($a$,$ b $,$ tmp$)$

begin

tmp ;

tmp tmp or a;

tmp tmp or b;

y tmp;

end process;

$```$

Select one:

True

False