The following data shows two processors and their read/write operations on two different words of a cache block X (initially X[0] = X[1] = 0). Assume the size of integers is 32 bits.

P1: X[0] ++; X[1] = 3;

P2: X[0] = 5; X[1] += 2;

a) List the possible values of the given cache block for a correct cache coherence protocol implementation. List at least one more possible value of the block if the protocol doesn't ensure cache coherency.

b) For a snooping protocol, list a valid operation sequence on each processor/cache to finish the above read/write operations.

c) What are the best-case and worst-case numbers of cache misses needed to execute the listed read/write instructions?