The following instructions are executed sequentially on a MIPS processor. Assume a non-interlocked pipeline:

#1 LD R3, 3(R1)

#2 LD R1, 2(R2)

#3 ADD R1, R2, #1

#4 SUB R2, R3, R1

#5 SD R2, 0(R1)

a. Identify a data dependence, anti-dependence and output dependence (if any) in the above code

b. Between which instructions are no-ops inserted? Use the attached diagram for assistance.

c. In the table below, write every case of:

i. Data forwarding

ii. Register write-read in one clock cycle

Enter the following data:

i. CC - The clock cycle when the data forwarding or register write-read is performed

ii. Src - The Interstage register or Register providing the data

iii. Dest Instr # - The stage or register receiving the data

iv. Value - The forwarded data

CC	Src (ISR or Reg)	Dest (Stage or Reg)	Value

Repeat the above question for the following set of instructions:

#1 SD R2, 0(R2)

#2 LD R2, 4(R1)

#3 SD R2, 3(R1)

#4 INC R1 //Increment R1

#5 SUB R2, R1, R5

CC	Src (ISR or Reg)	Dest (Stage or Reg)	Value