The following instructions are executed sequentially on a MIPS processor. Assume a non-interlocked pipeline:

#1 LD R3, 3(R1)

#2 LD R1, 2(R2)

#3 ADD R1, R2, #1

#4 SUB R2, R3, R1

#5 SD R2, 0(R1)

a. Identify a data dependence, anti-dependence and output dependence (if any) in the above code

(what's an easy way to identify this? )

b. Between which instructions are no-ops inserted? Use the attached diagram for assistance.

c. In the table below, write every case of: i. Data forwarding ii. Register write-read in one clock cycle

Enter the following data: i. CC - The clock cycle when the data forwarding or register write-read is performed ii. Src - The Interstage register or Register providing the data iii. Dest Instr # - The stage or register receiving the data iv. Value - The forwarded data

CC Src (ISR or Reg) Dest (Stage or Reg) Value Program execution order (in instructions) ISR1 DM Reg UL9 ALU/ DM ISR4 Reg CC Src (ISR or Reg) Dest (Stage or Reg) Value Program execution order (in instructions) ISR1 DM Reg UL9 ALU/ DM ISR4 Reg