The following synchronizer has two versions - one with divide by one counter and other with divide by two counter - draw the detailed waveform and correlate the timing parameters on the waveform to MTBF's equation to explain why divide by two counter will have better MTBF?

Your waveform should show the included signals - CLOCK, CLOCKN, ASYNCIN, META, SYNCIN

synchronizer 1 SYNCIN ASYNCIN (asynchronous input) Dob CLK CLK Synchronous system FF2 FF1 CLOCKN CLOCK (system clock) divide-by-N counter synchronizer 1 SYNCIN ASYNCIN (asynchronous input) Dob CLK CLK Synchronous system FF2 FF1 CLOCKN CLOCK (system clock) divide-by-N counter