The image here shows instruction memory from address $00000\mathrm{.}01BA-1D0$ in a $2$byte per row format. The table below represents the instruction register map for a $3$stage pipeline across six processor cycles at a point in time we'll call cycle $0.$ Assume the PC holds a current $($cycle $0)$ instruction fetch address of $00000\mathrm{.}01C6.$ Assume all instructions are $16$ bits stored little endian. Follow the steps below to fill in the information requested within the proper cells of the instruction register map. In each step, you should add at least one instruction $($in hex, can ignore the $0$x prefix$)$ to the table.

a$)$ What $16-$bit instruction value $($in hex$)$ is held in the cycle $0$ Fetch register?

b$)$ When is this instruction in the Decode register?

c$)$ When is it in the Execute register?

d$)$ Repeat a$)-$c$)$ above for the instruction fetched in cycle $1.$

e$)$ Repeat a$)-$c$)$ above for the instruction fetched in cycle $-1.$

$\backslash$table$[[$ss$,$dat,$],[00\mathrm{.}01B8,$B$4,\backslash$table$[[$A$2]]],[00\mathrm{.}01BA,Co,6F$