The multiplexer elaborates the overflow $(V)$ condition while shifting of $4-$bit register. What signals should be provided to the $s_4..s_0$ lines?

Select one or more:

a$.$ condition $C$ after shift

b$.$ bit $b_1$ of the register

c$.$ shift through C$/$ not through C

d$.$ bit $b_0$ of the register

e$.$ alternative of some bits of the register

f$.$ condition C before shift

g$.$ bit $b_3$ of the register

h$.$ shift left$/$right

i$.$ shift logical$/$arithmetic

j$.$ shift cyclic$/$not cyclic

k$.$ bit $b_2$ of the register