Question: The processor is converted into an 8-stage pipeline with 5 stages. It takes 125 ps to navigate the circuits in each stage. Assume that latches

The processor is converted into an 8-stage pipeline with 5 stages. It takes 125 ps to navigate the circuits in each stage. Assume that latches do not introduce a noticeable delay overhead.

a) What is the clock speed of this processor?

b) What is the CPI of this processor, assuming that every load/store instruction finds its instruction/data in the instruction or data cache, and there are no stalls from data/control/structural hazards?

c) What is the throughput of this processor (in billion instructions per second)?

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