Question: Please show all work. The processor in Q1 above is converted into an 8-stage pipeline, similar to the one discussed in class with 5 stages.

Please show all work. Please show all work. The processor in Q1 above is converted

The processor in Q1 above is converted into an 8-stage pipeline, similar to the one discussed in class with 5 stages. It takes 125 ps to navigate the circuits in each stage. Assume that latches do not introduce a noticeable delay overhead. 1. What is the clock speed of this processor? 2. What is the CPI of this processor, assuming that every load/store instruction finds its instruction/data in the instruction or data cache, and there are no stalls from data/control/structural hazards? 3. What is the throughput of this processor (in billion instructions per second)

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