The program has been compiled in MIPS assembly code assuming that registers $t6 and $t7 have been initialized with values 0 and 4 N respectively. The symbols VECTA and VECTB are 16-bit constant. The processor clock frequency is 1 GHz.

FOR beq $t6, $t7, END # if ($t6 == $t7) goto END lw $t2,VECTA($t6) # $t2 <- VECTA [$t6]; lw $t3,VECTB($t6) # $t3 <- VECTB [$t6]; add $t2,$t2,$t3 # $t2 <- $t2 + $t3; sw $t2,VECTA($t6) # VECTA[$t6] <- $t2; addi $t6,$t6,4 # $t6 <- $t6 + 4; j FOR # goto FOR; END:

Assume that the above MIPS instructions will be executed on a 5-stage pipelined processor

Apply loop unrolling (as well as instruction re-ordering, if you like) on the above MIPS code for two iterations. Write the corresponding MIPS instruction code.