The Register described in the below VHDL Code: entity shift_reg is port ( clock, Sin: in std_logic; Sout: out std_logic); end shift_reg; architecture behav of shift_reg is signal temp: std_logic_vector (7 down to 0); begin process (Clock) begin if (clock'event and clock='1') then for i in 0 to 6 loop Select one: O a. O b. O c. O d. end behav; temp (i+1)