$1.$ Create the VHDL files provided by in appendix A adding them to your VHDL

project $($Remember you need only one project for the entire course$).$

$2.$ Fully comment the code provided in appendices A and B$.$

$3.$ Obtain the RTL schematics of the Instruction Fetch stage, and each of its

components. Write down the differences between these schematics and the ones

in Figure $1.$

$4.$ Translate the code shown in the listing $5\mathrm{.}1$ to binary using the basic instruction

formats shown in Figure $3$ and fill the two leftmost columns of Table $1,$ with the

register letters u$,$ v$,$ w$,$ x$,$ y resolved to their equivalent numbers as explained

below.

Listing $5\mathrm{.}1$: Assembly Code

start: lw Ru$,4($R$0)$

lw Rv$,8($R$0)$

add Rw$,$ Ru$,$ Rv

sub Rx$,$ Ru$,$ Rv

sw Rx$,12($R$0)$

slt Ry$,$ Ru$,$ Rv

beq Ru$,$ Ru$,$ start

where u is the first non$-$zero digit of your id number, v is the second nonzero digit of

your id number, w is the third nonzero digit of your id number, and x is the fourth non

zero digit of your id number, and y is a random number between $10$ and $31.$

$5.$ Create a test bench file and run a simulation showing the operation of the instruction

fetch stage. You must first load your program $($Listing $5\mathrm{.}1)$ binary instructions obtained

in the previous step, into the instruction memory in order to have instructions to fetch.

To do that follow the sample test bench file shown in appendix B$.$ Your simulation

should look similar to the one in Figure $4,$ only that it should include all instructions to

be loaded and fetched. Explain the results of that simulation using annotations on the

timing diagram. Figure $4$: IF simulation timing diagram for $2$ instructions. Source: Generated using Xilinx Vivado

Table $1$: Instructions

Instructions loaded to IM Output Port Signals from Simulation

Assembly Hexadecimal Clock Cycle Instruction $($hex$)$ PC$+4($hex$)$

Appendix: A: Code

Listing A$\mathrm{.}1$: Instruction Fetch Stage Code

use IEEE.STD$\_$LOGIC$\_1164.$ALL;

use IEEE.STD$\_$LOGIC$\_$ARITH.ALL;

use IEEE.STD$\_$LOGIC$\_$UNSIGNED.ALL;

entity IFetch is

Port $($ clock, Resetn, branch : in STD$\_$LOGIC;

read, write : in STD$\_$LOGIC;

PC$\_$out, PCmas$4$ : out STD$\_$LOGIC$\_$VECTOR $(31$ downto $0)$;

data$\_$input: in STD$\_$LOGIC$\_$VECTOR $(31$ downto $0)$;

branch$\_$address : in STD$\_$LOGIC$\_$VECTOR $(31$ downto $0)$;

Instruction: out STD$\_$LOGIC$\_$VECTOR $(31$ downto $0))$;

end IFetch;

architecture Behavioral of IFetch is

signal PC$\_$in$,$ PC$,$ PC$\_$plus$\_4$ : std$\_$logic$\_$vector$(31$ downto

$0)$:$=($others$=>\text{'}0\text{'})$;

component mem$\_$module is $--$For $2^$N$-1$ words

generic$($N: integer:$=8)$;

Port $($ clock: in std$\_$logic;

address : in STD$\_$LOGIC$\_$VECTOR $($N$-1$ downto $0)$;

data$\_$input: in STD$\_$LOGIC$\_$VECTOR $(31$ downto $0)$;

data$\_$output: out STD$\_$LOGIC$\_$VECTOR $(31$ downto $0)$;

Read, write: in STD$\_$LOGIC$)$;

end component;

component mux$\_2\_1\_32$bits is

port$($

input$0$ : in std$\_$logic$\_$vector$(31$ downto $0)$;

input$1$ : in std$\_$logic$\_$vector$(31$ downto $0)$;

output : out std$\_$logic$\_$vector$(31$ downto $0)$;

control : in std$\_$logic$)$;

end component;

component registron is

Generic $($N: integer:$=32)$;

Port $($ clock, enable : in std$\_$logic;

D : in STD$\_$LOGIC$\_$VECTOR $($N$-1$ downto $0)$;

Q : out STD$\_$LOGIC$\_$VECTOR $($N$-1$ downto $0)$;

Resetn : in STD$\_$LOGIC$)$;

end component;

begin

PC$\_$outPC;

Instruction$\_$Memory: mem$\_$module generic map$($N$=>8)$

port map$($ clock,

PC$(7$ downto $0),$

data$\_$input,

Instruction,

read,

write$)$;

PC$\_$reg: registron generic map $($N$=>32)$

port map$($ clock,

resetn,

PC$\_$in$,$

PC$,$

resetn$)$;

branch$\_$mux : mux$\_2\_1\_32$bits port map $($PC$\_$plus$\_4,$

branch$\_$address,

PC$\_$in$,$

branch$)$;

PC$\_$plusPC$+4$;

PCmasPC$\_$plus$\_4$;

end Behavioral;

Memory Module

Listing A$\mathrm{.}2$: Memory Module Code

library IEEE;

use IEEE.STD$\_$LOGIC$\_1164.$ALL;

use IEEE.STD$\_$LOGIC$\_$ARITH.ALL;

use IEEE.STD$\_$LOGIC$\_$UNSIGNED.ALL;

entity mem$\_$module is

generic$($N: integer:$=8)$; $--$For $2^$N$-1$ bits

Port $($clock: in std$\_$logic;

address : in STD$\_$LOGIC$\_$VECTOR $($N$-1$ downto $0)$;

data$\_$input: in STD$\_$LOGIC$\_$VECTOR $(31$ downto $0)$;

data$\_$output: out STD$\_$LOGIC$\_$VECTOR $(31$ downto $0)$;

Read, write: in STD$\_$LOGIC$)$;

end mem$\_$module;

architecture Behavioral of mem$\_$module is

type mem is array $(2**($N$-2)-1$ downto $0)$ of std$\_$logic$\_$vector$(7$

downto $0)$;

signal mem$0$ : mem:$=($others$=>($others$=>\text{'}0\text{'}))$;

signal mem$1$ : mem:$=($others$=>($others$=>\text{'}0\text{'}))$;

signal mem$2$ : mem:$=($others$=>($others$=>\text{'}0\text{'}))$;

signal mem$3$ : mem:$=($others$=>($others$=>\text{'}0\text{'}))$;

signal address$\_$internal :integer range $0$ to $2**($N$-2)-1$;

signal data$\_$out$\_$int :STD$\_$LOGIC$\_$VECTOR $(31$ downto $0)$;

begin

address$\_$internalconv$\_$integer$($address$($N$-1$ downto $2))$;

data$\_$outputdata$\_$out$\_$int;

data$\_$out$\_$int mem$0($address$\_$internal$)$ &

mem$1($address$\_$in