The VHDL code for two 1 bit tristate buffers driving a 1 bit bus is shown 1 LIBRARY IEEE 2 USE ieee std logic 1 1 6 4 all 3 ENTITY eece IS 4 PORT ( x , en IN STD LOGIC VECTOR ( 1 DOWNTO 0 ) 5 y OUT STD LOGIC ) 6 END 7 ARCHITECTURE eece arch OF eece IS 8 BEGIN 9 WITH en ( 0 ) SELECT 1 0 y x ( 0 ) WHEN ' 0 ' , 1 1 ' Z ' WHEN OTHERS 1 2 1 3 WITH en ( 1 ) SELECT 1 4 y x ( 1 ) WHEN ' 0 ' , 1 5 ' Z ' WHEN OTHERS 1 6 END Write the VHDL code that implements 2 5 6 1 bit tristate buffers driving a 1 bit bus To ensurethere is no syntax errors and correct operations, use the Altera tools to simulate your code

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Question: The VHDL code for two 1 - bit tristate buffers driving a 1 - bit bus is shown . 1 LIBRARY IEEE; 2 USE ieee.std

The VHDL code for two

1 -

bit tristate buffers driving a

1 -

bit bus is shown

. 1

LIBRARY IEEE;

2

USE ieee.std

_

logic

_1164 .

all;

3

ENTITY eece IS

4

PORT

(

,

en : IN STD

_

LOGIC

_

VECTOR

(1

DOWNTO

0)

;

5

y : OUT STD

_

LOGIC

)

;

6

END;

7

ARCHITECTURE eece

_

arch OF eece IS

8

BEGIN

9

WITH en

(0)

SELECT

10

< =

(0)

WHEN

' 0', 11'

'

WHEN OTHERS;

1213

WITH en

(1)

SELECT

14

< =

(1)

WHEN

' 0', 15'

'

WHEN OTHERS;

16

END;Write the VHDL code that implements

256 1 -

bit tristate buffers driving a

1 -

bit bus. To ensurethere is no syntax errors and correct operations, use the Altera tools to simulate your code.

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