This circuit is called parallel-in-serial-out. Fill in the blanks (dashed lines) in the given VHDL codes which is for entity declaration and architecture, with the size of the output bus, w, treated as a generic with the default value equal to 8.

library ieee; use ieee.std_logic_1164.a11; entity piso is generic ( w : integer := ); port 1 clk : in std logic; ena : in stdagic; load : in std logic; rst : in std logic: x : in std logic vector (.............. downto 0); y : out std logic vector (w1 downto 0)); end piso; architecture behavioral of piso is type bus array is array (3 downto 0) of std 1 ogic vector (w-1 downto 0); signal reg, mux : bus array; begin mux(3)