This exercise examines the effect of different cache designs, specifically comparing associative caches to the direct-mapped caches. Assume the memory is word addressing with 8-bit addresses and the cache is a fully associative cache with two-word blocks and a total size of eight words. Assume one word is 32 bits. - The number of blocks in the cache is blocks. - The number of sets in the cache is set(s). - The number of blocks in the memory is blocks. - The number of tag bits in each block is bits. - The total bits required to implement the cache is bits. For this exercise, refer to the sequence of word address shown below. Ox03, 0xb4, 0x2b, 0x02, 0xbe, 0x58, 0xbf, 0x0e, 0x1f, 0xb5, 0xbf, 0xba, 0x2e, 0xce Assume a true LRU replacement policy. For each reference, identify: the binary word address, the tag, whether the reference is a hit or a miss. \begin{tabular}{|c|c|c|c|c|} \hline Word Address in Hex & Word Address in Binary & Tag in Binary & Hit or Miss & Contents \\ \hline 0x03 & 00000011 & 0000001 & M & \\ \hline 0xb4 & & & & \\ \hline 0x2b & & & & \\ \hline 0x02 & & & & \\ \hline 0xbf & & & & \\ \hline 0xbe & & & & \\ \hline \end{tabular} - After these accesses, Is the cache full? (yeso) - How many replacements did occur