This exercise examines the effect of different cache designs, specifically comparing associative caches to the direct-mapped caches from Section 5.4. For these exercises, refer to the sequence of word address shown below.0x03, 0xb4, 0x2b, 0x02, 0xbe, 0x58, 0xbf, 0x0e, 0x1f, 0xb5, 0xbf, 0xba, 0x2e, 0xce

1. Sketch the organization of a three-way set associative cache with two-word blocks and a total size of 48 words. Your sketch should have a style similar to Figure 5.18 but clearly show the width of the tag and data fields.

2. Trace the behavior of the cache from Exercise 5.11.1.
Assume a true LRU replacement policy. For each reference, identify 

• The binary word address, 
• The tag, 
• The index, 
• The offset, 
• Which tags are in each way of the cache after the reference has been handled.

3. Sketch the organization of a fully associative cache with one-word blocks and a total size of eight words. Your sketch should have a style similar to Figure 5.18 but clearly show the width of the tag and data fields.

4. Trace the behavior of the cache from Exercise 5.11.3.
Assume a true LRU replacement policy. For each reference, identify 

• The binary word address, 
• The tag, 
• The index, 
• The offset, 
• Whether the reference is a hit or a miss, and 

The contents of the cache after each reference has been handled.

5. Sketch the organization of a fully associative cache with two-word blocks and a total size of eight words. Your sketch should have a style 

similar to Figure 5.18 but clearly show the width of the tag and data fields.

6. Trace the behavior of the cache from Exercise 5.11.5.

Assume an LRU replacement policy. For each reference, identify 

• The binary word address, 
• The tag, 
• The index, 
• The offset, 
• whether the reference is a hit or a miss, and 
• The contents of the cache after each reference has been handled.

7. Repeat Exercise 5.11.6 using MRU (most recently used) replacement.

8. Repeat Exercise 5.11.6 using the optimal replacement policy (i.e., the one that gives the lowest miss rate).

Figure 5.18

Tag Index V Tag 0 1 2 253 254 255 Address 31 30 12 11 10 9 8-3210 Data Index 22 8 V Tag Data Hit V Tag Data V Tag (4-to-1 multiplexor) Data 22 Data 32