This exercise is intended to help you understand the relationship between control hazards and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor: 1w r2, 0 (r1) begr2, ro, label2 #not taken once, then taken 1w r3, 0 (r2) beqr3, ro, label! #taken add rl, r3, rl sw rl, 0 (r2) labell: labe12: Draw the pipeline execution diagram for this code, assuming branches execute in the ID stage (means resolve in the EX stage). Assume there is a branch target buffer so that we know the branch target address during the fetch stage. This exercise is intended to help you understand the relationship between control hazards and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a 5-stage pipeline, full forwarding, and a predict-taken branch predictor: 1w r2, 0 (r1) begr2, ro, label2 #not taken once, then taken 1w r3, 0 (r2) beqr3, ro, label! #taken add rl, r3, rl sw rl, 0 (r2) labell: labe12: Draw the pipeline execution diagram for this code, assuming branches execute in the ID stage (means resolve in the EX stage). Assume there is a branch target buffer so that we know the branch target address during the fetch stage