$8.$ This exercise is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a $5-$stage pipeline, full forwarding, and a predict$-$taken branch predictor:

lw r$2,0($r$1)$

label$1$: beq r$2,$r$0,$label$2\backslash$# not taken once, then taken

lw r$3,0($r$2)$

beq r$3,$r$0,$label$1\backslash$# taken

add r$1,$r$3,$r$1$

label$2$: sw r$1,0($r$2)$

a$.$ Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage.

b$.$ Repeat $8$ a $,$ but assume that delay slots are used. In the given code, the instruction that follows the branch is now the delay slot instruction for that branch.

c$.$ One way to move the branch resolution one stage earlier is to not need an ALU operation in conditional branches. The branch instructions would be "bez rd$,$label" and "bnez rd$,$label", and it would branch if the register has and does not have a zero value, respectively. Change this code to use these branch instructions instead of beq. You can assume that register R$8$ is available for you to use as a temporary register, and that an seq $($set if equal$)$ R$-$type instruction can be used.