$1.$ This exercise is intended to help you understand the relationship between delay slots, control hazards, and branch execution in a pipelined processor. In this exercise, we assume that the following MIPS code is executed on a pipelined processor with a $5-$stage pipeline and a predict$-$taken branch predictor. We don't have forwarding:

a$)(1)$ What is the branch delay slot? $(2)$ What is the usage of it in the MIPS hardware? $(10$pts$)$

b$)(1)$ Draw the pipeline execution diagram for this code and $(2)$ explain why, assuming there are no delay slots and that branches execute in the EX$-$stage. $(30$ pts$)$

c$)$ One way to move the branch resolution one stage earlier is to not need an ALU operation in conditional branches. The branch instructions would be "bez rd$,$ label" and "bnez rd$,$ label", and it would branch if the register has and does not have a zero value, respectively. Change this code to use these branch instructions instead of "beq". You can assume that register r$8$ is available for you to use as a temporary register, and that an "seq" $($set if equal$)$ R$-$type instruction can be used. $(10$ pts$)$