This exercise is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequence of instructions, and that it is executed on a 5 stage pipelined datapath: add r5, r2, r1 |w r3, 4 (r5) |w r2, 0 (r2) or r3, r5, r3 sw r3, 0 (r5) A) If there is no forwarding or hazard detection, insert nops to ensure correct execution. B) Repeat A, but now use nops only when a hazard cannot be avoided by changing or rearranging these instructions. You can assume register r7 can be used to hold temporary values in your modified code. C) If the processor has forwarding, but we forget to implement the hazard detection unit, what happens when this code executes? D) If there is forwarding, for the first 5 cycles during the execution of this code, specify which signals are asserted in each cycle by hazard detection and forwarding units in figure 4.60 This exercise is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequence of instructions, and that it is executed on a 5 stage pipelined datapath: add r5, r2, r1 |w r3, 4 (r5) |w r2, 0 (r2) or r3, r5, r3 sw r3, 0 (r5) A) If there is no forwarding or hazard detection, insert nops to ensure correct execution. B) Repeat A, but now use nops only when a hazard cannot be avoided by changing or rearranging these instructions. You can assume register r7 can be used to hold temporary values in your modified code. C) If the processor has forwarding, but we forget to implement the hazard detection unit, what happens when this code executes? D) If there is forwarding, for the first 5 cycles during the execution of this code, specify which signals are asserted in each cycle by hazard detection and forwarding units in figure 4.60