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Q1a) A Microprocessor With L1 and L2 cache, The access times of Li and L2 cha Caches are 1 and 6 clock Cycles respectively, The miss penalty of L2 cache is 20 clock Cycles. The miss rate of L1 cache is twice That of L2 . The average memory access Time of the cache system is y cycles. Calculate the miss rates of 11 and L2 caches? State the different causes of Cache misses and how to reduce each one 2 In a multi-core System, what are the Pros/Cons to a shared L2 Cane? @ Draw MLC type EEPROM flash memory Cell and explain how to read it